1. Technical Field
The present disclosure relates to phase interpolation, and more particularly relates to a phase interpolation circuit and method that is capable of operating in a low voltage and capable of preventing a 3-code dithering.
2. Discussion of Related Art
As semiconductor technology has developed, digital technology for devices such as personal computers, portable digital assistants or mobile communications devices has been similarly developed.
However, despite improvements in data transmission rates and in operation rates of peripheral devices such as memory, communication devices or graphic devices, the operation rate of many peripheral devices is not capable of keeping up with an operation rate of a microprocessor. Thus, there is a rate difference between new microprocessors and their peripheral devices. Accordingly, in high technology digital industries, there is a desire for a significant improvement in operation rates of peripheral devices.
For example, in a method of transmitting data by synchronizing the data with the clock signal, such as the data transmission between a memory device and a memory controller, a bus load becomes large and a transmission frequency becomes high. Accordingly, it is very important to make synchronization between the clock signal and data. For this purpose, there are a phase lock loop (PLL) circuit and a delay lock loop (DLL) circuit.
Generally, the phase lock loop circuit and delay lock loop circuit comprise a phase interpolation circuit. The phase interpolation circuit is a circuit that controls two clock signals having different phases to generate a clock signal between the two clock signals. The phase interpolation circuit is capable of outputting an accurate desired phase that may be applied to various circuits. The delay lock loop circuit is typically used in semiconductor memory devices. An example of a conventional delay lock loop circuit, including a phase interpolation circuit, is shown in FIG. 1.
Referring to FIG. 1, the example of a conventional delay lock loop circuit comprises a reference loop 10, a phase selection unit 20, an interpolation unit 30, a phase detection unit 40 and a control unit 50. The conventional delay lock loop circuit may further comprise a duty cycle correction circuit configured to correct a duty cycle of an output signal of the interpolation unit 30 to obtain the duty cycle with a preset level, such as 50%, for example.
The reference loop 10 generates a plurality of reference clock signals by delaying the exterior clock signal (C, Cb) through a plurality of delay units, which respectively have corresponding delays obtained by uniformly dividing a period (T) of the exterior clock signals (C, Cb) by the number of the delay units.
For example, in case the period (T) of the respective exterior clock signal (C, Cb) is divided by 8, a delay unit delays the exterior clock signal (C, Cb) by T/8. Accordingly, a signal through one delay unit is delayed by T/8, and a signal through two delay units is delayed by T/4, and a signal through n delay units (n is a natural number which is more than one) is delayed by nT/8, compared to the exterior clock signal (C, Cb). Therefore, a plurality of reference clock signals having different delays is outputted.
The phase selection unit 20 includes at least one phase multiplexer (mux) circuit. The phase mux circuits are controlled by selection control signals (SEL) outputted from the control unit 50. Each of the phase mux circuits is configured to select two reference clock signals among the reference clock signals, the two clock signals being the closest and the second closest clock signal to the exterior clock signal (C, Cb), in response to the same selection control signals (SEL) received by the control unit 60.
The interpolation unit 30 includes at least one phase interpolation circuit. The phase interpolation circuit generates a phase interpolation signal having any phase between those of the two reference clock signals, which are selected by the phase selection unit 20, in response to an interpolation control signal (VCNA, VCNB) received by the control unit 60.
The phase detection unit 40 compares phases of the phase interpolation signal and the exterior clock signal (C, Cb), and applies a detection signal (PHADV) corresponding to the difference of the phases to the control unit 60. The control unit 50 includes a Finite State Machine (FSM) circuit having a counter circuit and a D/A converter circuit, and generates the control signals for selection (SEL) and interpolation (VCNA, VCNB) in response to the detection signal (PHADV) received by the phase detection unit 40, thereby controlling the phase selection unit 20 and the interpolation unit 30.
The operation as described above continues until the dithering phenomenon occurs in the phase detection unit 40, and a signal generated in the dithering phenomenon is a phase interpolation signal. This state of the signal generation is called a state of “being locked”.
An example of a conventional phase interpolation circuit constituting the interpolation unit of FIG. 1 is disclosed in U.S. Pat. No. 6,359,486. However, the phase interpolation circuit shown in FIG. 6 of U.S. Pat. No. 6,359,486 has a problem as follows. Given a current source controlled by a first control signal (VC) and a current source controlled by a second control signal (VCB), in case either current source is not operated and the other current source is operated, an input signal from the inoperative current source should not affect the output signal. Unfortunately, in a case where a current source controlled by the first control signal VC is not operative, the first input signal (Φ0) affects the output signal (OUT, OUTB) by a capacitive coupling of a transistor to which the first input signal is inputted, thereby making an error of phase shift. In addition, in a case where the load comprises a transfer gate circuit and the current source for constituting a unit cell comprises a transistor, 4 transistors are connected in series, thereby increasing the number of transistors that operate in saturation and making a problem where operation at a low voltage has a limitation.
FIG. 2 is a circuit diagram illustrating another phase interpolation circuit according to the conventional art. This conventional phase interpolation circuit includes loads (L1, L2), transistors (NM1-NM4, N1-N6), and has a connection structure as shown in FIG. 2.
The phase interpolation circuit of FIG. 2 operates to isolate input signals and output signals by arranging the transistors (NM1-NM4) for operating as current sources between output nodes (OUT, OUTb) and the transistors (N1-N4), which receive input signals (S1, S1b, S2, S2b).
This circuit does not show the capacitive coupling effect of the phase interpolation circuit shown in FIG. 6 of U.S. Pat. No. 6,359,486. However, it has a large size layout and a varying total load, thereby making the phase shift nonlinear. In addition, 4 transistors are connected in series, thereby increasing the number of transistors that operate in saturation areas, still making the problem where an operation of the circuit in a low voltage has a limitation.
FIG. 3 is a graph for showing a 3-code dithering phenomenon which is another problem resulting from the conventional phase interpolation circuit. FIG. 3 shows a change of phase according to time, resulting from the dithering phenomenon in the phase detection unit 40 of FIG. 1.
As shown in FIG. 3 for a digital control method, the phase is discrete and it is not possible to achieve a locking operation without error. It is typical to perform the locking operation when an output signal is dithering between two adjacent phases with reference to a reference phase as shown in a dotted area 12 (i.e. 2 code dithering). However, in case any one of phases is in an uncertain area of the phase detection unit (40 of FIG. 1) or any one of phases exactly corresponds to the reference phase, there is a problem where the output signal is dithering at three phases as shown by a dotted area 14 of FIG. 3 (i.e., 3-code dithering).